1. Technical Field
The disclosure relates generally to the field of consumer electronics devices, as well as networks thereof. More particularly, in one exemplary aspect, the disclosure is directed to methods and apparatus for implementing a synchronized multi-directional transfer on an inter-device (e.g., inter-processor communication (IPC)) link between two (or more) independently operable devices such as processors. Various aspects of the present disclosure are directed to, inter alia, run-time processing, power management, and/or flow control of data transfers.
2. Description of Related Technology
Many electronic devices, such as e.g., mobile devices and portable computing devices, include integrated circuits (ICs) such as e.g., an Application Processor (AP) system on a chip (SoC), which is a main processor chip designed to support one or more applications running in the operating environment of the electronic device (e.g., host processor). The AP is in data communication with other peripheral chipsets (e.g., processors) of the device, such as e.g., cellular and/or Wi-Fi chipsets via a memory-mapped interconnect and/or bus.
Various bus architectures and techniques have evolved over time which enable handling of increasingly faster data rates and provide higher levels of data throughput for the AP and/or peripheral processors. One such example is Peripheral Component Interconnect Express (PCIe); see e.g., PCI Express Base Specification Revision 3.1 dated Oct. 8, 2014. PCIe is a high-speed serial computer expansion bus standard designed to replace older PCI and similar bus standards. In terms of architecture, PCIe is based on point-to-point connectivity with separate serial links connecting each endpoint peripheral component (e.g., graphics card, memory, Wi-Fi, cellular, etc.) to the root complex or host processor (including the AP).
Communication between the AP and the peripheral chipsets via PCIe has many desirable attributes in terms of, inter alia, performance and flexibility. However, PCIe (as well as some other existing “computer-centric” bus technologies) suffer certain disabilities, especially from the standpoint of portable consumer electronic device implementations. Specifically, as noted above, extant PCIe technologies were developed for use within desktop, server, and laptop computers, which are to varying degrees agnostic to many electrical power considerations affecting smaller portable devices. Desktops and servers (and to a lesser degree laptops) are less concerned with electrical power consumption/conservation, and more concerned with bus performance, ability to “hot plug”, and the like. Accordingly, implementing a technology such as PCIe which, in its current incarnation, both (i) consumes significant electrical power during operation, and (ii) has limited power management infrastructure (e.g., application or host processor and chipset “sleep” states, and management of data and transactions during such sleep states), is generally unsuitable for portable consumer electronics applications where power consumption and battery conservation are critical (such as e.g., cellular- and Wi-Fi-enabled smartphones, tablets, “phablets”, portable media players, etc.). Further, other device components, such as the AP and the peripheral chipsets each consume additional electrical power during operation.
In order to limit power consumption within the electronic device, both of the AP and the peripheral chipsets may be automatically and independently switched between one or more lower power states (e.g., an awake-low power state, a sleep-low power state, etc.) during periods of non-use and a higher power state (e.g., an awake-high power state) during periods of use. In some instances, activity or communication between the AP and the peripheral chipsets can initiate switching from a lower power state to a fully awake state (e.g., an awake-high power state). For example, activity or communication from the AP, such as e.g., an uplink request, can initiate switching of the peripheral chipset in a lower power state to a fully awake state and/or activity or communication from the peripheral chipset, such as e.g., a downlink request, can initiate switching of the AP in a lower power state to a fully awake state. Because existing PCIe operation does not consider power saving states during transactions, an untimely PCIe transaction may prevent a processor from entering a power saving state or cause an unnecessary exit from a power saving state.
Hence, there is a need for improved apparatus and associated methods which can leverage the high data throughput and other desirable attributes of bus technologies such as PCIe (and other “memory mapped” technologies), yet support the requirements of rigorous power management and conservation.